OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.
Miquel Moreto is an Associate Professor at the Computer Architecture Departament (DAC) of the Universitat Politècnica de Catalunya (UPC), and he leads the High Performance Domain Specific Architectures team at the Barcelona Supercomputing Center (BSC). Miquel received the PhD from UPC in 2010. After finishing the PhD, he spent 15 months at the International Computer Science Institute (ICSI), affiliated with UC Berkeley, as a Fulbright Postdoctoral Research Fellowship Holder during 2011 and 2012. In 2013, he returned to Barcelona to work on multiple European projects (RoMoL, Mont-Blanc, EPI, DeepHealth, eProcessor) and industrial projects (Arm, IBM, Lenovo). Miquel has published over 125-refereed conference and journal papers and co-advised 12 PhD students. In 2019, he led the design and fabrication of Lagarto, the first academic processor developed in Spain based on the open source RISC-V instruction set architecture. Finally, he coordinates the DRAC project, which is promoting the Lagarto initiative with new generations of the processor and accelerators.
Charlie is CEO of Bluespec, Inc., a provider of high-level tools and IP for ASIC and FPGA design. Before Bluespec, he was general manager of Faraday Technology USA, a fabless ASIC company. Charlie has over 25 years of experience in marketing and developing RISC processors at Lexra, LSI Logic, Kendall Square Research and Commodore. Charlie received a Bachelor of Science from Johns Hopkins University and a Master of Science from the Massachusetts Institute of Technology.
Fabien Clermidy is currently heading the digital architecture and IC design department in the research technology division of CEA. In this position, he develops the hardware and software computing strategy for High-Performance Computing, Artificial Intelligence, Cybersecurity and Cyber-Physical-Systems in relation with system developments in automotive, factory of future, avionics or defense and new nanotechnologies such as 3D chip-stacking, embedded Non-Volatile-Memories, photonic and quantum computing. Fabien has been working in CEA since 2000, holding different positions as project leader and manager of different teams. He is also a senior expert with a Ph’D supervisor degree and has published more than 80 papers in the greatest conferences such as ISSCC or DAC.
Keith Hopkins is a serial entrepreneur. He started in Design with Intel and transitioned to Sales/Business Development for EDA, Consulting and Semiconductor IP licensing. Over the past 2 decades, he has worked with multiple early/mid stage companies as VP Sales/Business Development including ARM, Artisan, Denali, PLDA and EVE where he created comprehensive business strategies, developed the Sales/Business Plans, built the Sales teams and accelerated revenues leading to 4 company M&A exits with valuations in excess of $1.5B. He is currently an Executive Advisor, member of multiple Boards and the EVP of Sales and Business Development for Corelab Technology. He has been a part of CPU evolution from Intel to ARM and is excited to get a front row seat for the next stage by joining the OpenHW Board as the world explores RISC-V.
Liang Peng is Vice President, head of IC-Lab and head of HMS Ecosystem Development in Futurewei Technologies. In this role, Liang leads R&D, ecosystem development in IC design, and HMS ecosystem development. He has a professional career in the semiconductor industry for 20+ years in many Silicon Valley companies including Nvidia, Intel, Rambus. He has played leading roles in technology and product development as well as strategy planning and partnership from mobile to cloud at chip and system level on GPU, CPU, video processor, memory and SOC etc. His early pioneer work and invention at Nvidia on pixel shader architecture is an industry milestone for GPU, setting the foundation for programmable shading, massive parallel computing as well as convolutional neural network for deep learning with GPU. He is also advisor and former Chairman and President of CASPA (2012-13). Liang has a B.S. in Astrophysics from Peking University, and a Ph.D. in Electrical Engineering from Cornell University.
Flo serves as CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate on open source cores, related IP, tools and software projects. His primary mission is to accelerate the adoption of high-quality, open-source RISC-V cores in mainstream applications while making it accessible for newcomers to join the vibrant RISC-V ecosystem. Previously, Flo played a pivotal role as head of sales for EMEA and Japan at Andes Technology. He successfully introduced RISC-V CPU IP to leading multinational corporations and pioneered its adoption in emerging sectors, including automotive, medical, and security.
Davide is the OpenHW Group Director of Engineering, Cores Task Group and is a PhD candidate (Spring 2020) at the Integrated Systems Laboratory of ETH Zurich (Zurich, Switzerland) in the Digital Systems group Parallel Ultra Low Power (PULP) Platform under the supervision of Prof. Luca Benini. His main research focus is on low-power energy-efficient computer architectures under the PULP project for smart systems and human-machine interfaces. Davide’s main contributions to the PULP project have been:
Davide holds Bachelor and Master degrees in Computer Engineering from Politecnico di Torino, Italy.
Florian is the OpenHW Group Director of Engineering, HW & SW Task Groups and a PhD student at the Integrated Systems Laboratory of ETH Zurich. His research interests include exploring new directions in energy-efficient high-performance computing. He is also the principle architect of CVA6 (Ariane). His experience includes a strong background in physical design with more than eight ASICs designed, manufactured and tested. Florian holds a Bachelor of Science degree from TU Wien and a master’s degree from ETH Zurich. See the following link for further information. http://asic.ethz.ch/authors/Florian_Zaruba.html
Mario is a Verification Engineer, currently part of the Verification Task Group. He has extensive technical experience in Verification, mainly working on developing UVM environments for complex designs and doing coverage explorations to target non-stimulated parts of the design or dead code. Additionally, he has worked on developing features for Golden Models to extend their functionality and mimic the design. He holds a Computer Science degree and MIRI Master's from Universitat Politecnica de Catalunya, Spain.
Mike Thompson is the OpenHW Group Director of Engineering, Verification Task Group. He is a senior IC Functional Verification engineering manager with more than 20 years experience. Mike has led all aspects of the discipline with broad experience in simulation, emulation and prototyping plus management level experience of formal verification projects. He has both hands-on and management level experience with multiple SV/UVM projects and has developed teams driving SV/UVM for constrained-random, coverage driven verification efforts. Michael has been involved in a dozen successful tape-outs including five 100M gate-scale devices based on proprietary RISC processors which were verified using a novel random instruction generator and coverage model implemented in SV/VMM. Mike holds a Bachelor of Applied Science degree in Electrical and Electronics Engineering from the University of Regina, Canada.