Tuesday, Feb 15, 2022
OpenHW TV S03/E08Advancing RISC-V Processor Verification Oct 27, 2022 This OpenHW TV episode introduces the new Chair of the OpenHW Verification Task Group and the expanded charter to help support the growing RISC-V Verification Ecosystem. The OpenHW Group welcomes Simon Davidmann of Imperas Software, a founding member of OpenHW, as the new Chair of the OpenHW Verification Task Group (VTG). As part of the CORE-V roadmap, the VTG is updating the successful CORE-VERIF framework to address both the increasing design complexity and improve the DV efficiency for the anticipated bandwidth required for all the new CORE-V cores in development.
Thursday, Jan 28, 2021
OpenHW TV S02 E08CORE-V Cores & RISC-V Profiles Nov 12, 2021 As RISC-V evolves over time, the set of ISA features supported by each software ecosystem will also need to evolve over time, and new software ecosystems will be added. To manage this evolution, RISC-V is moving towards a model of regular annual delivery of a coherent set of ISA updates according to an ISA roadmap, and architecture profiles are intended to provide the natural structure for planning, packaging, and releasing these ISA updates.
Wednesday, Jul 8, 2020
OpenHW TV S01 E06Deep Dive into Formal Verification for the CORE-V CVE4 Nov 20, 2020 Our last webinar episode of 2020 is now available to watch on-demand. Last month we looked at our progress on the RTL functional freeze milestone for the CVE4 and how we arrived there with the high-quality verification work from our members. We had a lot of questions about the Formal Verification work carried out to get us this far, so we have dedicated this episode to a deep-dive into the Formal Verification work and to hear from our partners on what it actually means.
Monday, Jan 1, 0001
OpenHW TV S04/E02Destination: ASIC-Ready - Journey of the Open-Source Application-Class RISC-V Processor CVA6 Oct 24, 2023 This episode of OpenHW TV focuses on the incredible journey of the open-source RISC-V processor CVA6, from its inception as Ariane to its present state. The discussion covers its current features, supported configurations (e.g., multicore) accelerators (e.g., RISC-V Vector), and platforms. Details of the ongoing design improvements and rigorous verification work will be shared along with a demo of DOOM running on CVA6 (on an FPGA platform).